Arithmetic
Adds the value in reg8
and the carry flag to the value in a
. Also includes 1R cycle if reg8
is (hl)
.
Adds the value in reg8i
and the carry flag to the value in a
.
Adds the value pointed to by regi
+ ofs8
and the carry flag to the value in a
.
Adds the value in reg24
to the value in hl
.
- Opcode:
00
reg24
1001
Register Bit Field bc
00
de
01
hl
10
sp
11
- Bytes: 1
- Flags:
- H: Set if carry from bit 11, reset otherwise
- N: Reset
- C: Affected as defined
- Cycles: 1F
Adds the value in reg8
to the value in a
. Also includes 1R cycle if reg8
is (hl)
.
Adds the value in reg24
to the value in regi
.
- Opcode:
regi
00
reg24
1001
Index Bit Field ix
11011101
iy
11111101
Register Bit Field bc
00
de
01
ix
/iy
10
- Bytes: 2
- Flags:
- H: Set if carry from bit 11, reset otherwise
- N: Reset
- C: Affected as defined
- Cycles: 2F
Compares (via subtraction) the value in reg8
with the value in a
. Also includes 1R cycle if reg8
is (hl)
.
Compares (via subtraction) the value in reg8i
with the value in a
.
Compares (via subtraction) the value pointed to by regi
+ ofs8
with the value in a
.
This instruction is meant to be used after an addition or subtraction instruction on binary-coded-decimal values, specifically add
, adc
, inc
, sub
, sbc
, dec
, or neg
. Following one of these specific instructions, daa
adjusts the value in a
according to this table:
Operation | C flag prior to DAA | H flag prior to DAA | Upper digit of a |
Lower digit of a |
Number added to a |
C flag after DAA | H flag after DAA |
---|---|---|---|---|---|---|---|
ADD, ADC, or INC | 0 | 0 | 0 - 9 | 0 - 9 | 00 | 0 | 0 |
0 | 0 | 0 - 8 | A - F | 06 | 0 | 1 | |
0 | 1 | 0 - 9 | 0 - 3 | 06 | 0 | 0 | |
0 | 0 | A - F | 0 - 9 | 60 | 1 | 0 | |
0 | 0 | 9 - F | A - F | 66 | 1 | 1 | |
0 | 1 | A - F | 0 - 3 | 66 | 1 | 0 | |
1 | 0 | 0 - 2 | 0 - 9 | 60 | 1 | 0 | |
1 | 0 | 0 - 2 | A - F | 66 | 1 | 1 | |
1 | 1 | 0 - 3 | 0 - 3 | 66 | 1 | 0 | |
SUB, SBC, DEC, or NEG | 0 | 0 | 0 - 9 | 0 - 9 | 00 | 0 | 0 |
0 | 1 | 0 - 8 | 6 - F | FA | 0 | 0 | |
1 | 0 | 7 - F | 0 - 9 | A0 | 1 | 0 | |
1 | 1 | 6 - F | 6 - F | 9A | 1 | 0 |
- Opcode:
00100111
- Bytes: 1
- Flags:
- S: Set if msb of the result is 1, reset otherwise
- Z: Set if result is 0, reset otherwise
- H: See above table
- P/V: Detects parity
- C: See above table
- Cycles: 1F
Subtracts one from the value in reg24
.
- Opcode:
00
reg24
1011
Register Bit Field bc
00
de
01
hl
10
sp
11
- Bytes: 1
- Flags:
- None
- Cycles: 1F
Subtracts one from the value in regi
.
- Opcode:
regi
00101011
Index Bit Field ix
11011101
iy
11111101
- Bytes: 2
- Flags:
- None
- Cycles: 2F
Adds one to the value in reg24
.
- Opcode:
00
reg24
0011
Register Bit Field bc
00
de
01
hl
10
sp
11
- Bytes: 1
- Flags:
- None
- Cycles: 1F
Adds one to the value in regi
.
- Opcode:
regi
00100011
Index Bit Field ix
11011101
iy
11111101
- Bytes: 2
- Flags:
- None
- Cycles: 2F
Multiplies the low byte of reg24
by the high byte of reg24
. The 16-bit result is stored back into the register pair.
- Opcode:
11101101
01
reg24
1100
Register Bit Field bc
00
de
01
hl
10
sp
11
- Bytes: 2
- Flags:
- None
- Cycles: 2F + 4
Subtracts the value in reg8
and the carry flag from the value in a
. Also includes 1R cycle if reg8
is (hl)
.
Subtracts the value in reg8i
and the carry flag from the value in a
.
Subtracts the value pointed to by regi
+ ofs8
and the carry flag from the value in a
.
Subtracts the value in reg8
from the value in a
. Also includes 1R cycle if reg8
is (hl)
.